Chiplet Heterogeneous Integration Technology—Status and Challenges

TLDR

Chiplet-based design integrates heterogeneous dies into a single chip via advanced packaging, offering a promising solution to the stagnation of Moore’s law and Dennard scaling by enabling reuse of dies across process nodes, reducing design cost, cycle time, and complexity while improving yield. This review surveys industry efforts over the past decade, summarizing the concepts and techniques related to chiplets. The authors analyze industry developments to outline the concepts and techniques used in chiplet integration. The review concludes with a discussion and forecast of the future of chiplets.

Abstract

As a heterogeneous integration technology, the chiplet-based design technology integrates multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using advanced packaging technology, which is a promising way to tackle the failure of Moore’s law and Dennard scaling. Currently, as process nodes move forward, dramatically rising cost, design cycle, and complexity are driving industry to focus on the chiplets. Chiplets allows IC designers to merge dies fabricated at different process nodes and reuse them in different projects, which helps to reduce the cost during design and improve yield. In this review, we look back at the industry’s efforts over the past decade and summary the concepts and techniques associated with chiplets. In the end, a discussion and conclusion will be given to forecast the future of chiplets.