Dennard Scaling

Dennard Scaling is a physical scaling principle in semiconductor device engineering which states that as transistors are scaled to smaller dimensions, their power density remains constant, enabling proportional reductions in voltage, current, and power consumption with shrinking device size.

66

Publications

5.7K

Citations

233

Authors

88

Institutions

Publications per year

2017–2026

42

Authors

233

  1. KS
    Karthikeyan Sankaralingam

    University of Wisconsin–Madison, United States

    4 publications · 2.3K citations

    5

    h-index

  2. EB
    Emily Blem

    University of Wisconsin–Madison, United States

    4 publications · 2.3K citations

    4

    h-index

  3. HE
    Hadi Esmaeilzadeh

    Georgia Institute of Technology, United States

    4 publications · 2.3K citations

    4

    h-index

  4. RS
    Renée St. Amant

    The University of Texas at Austin, United States

    4 publications · 2.3K citations

    4

    h-index

  5. DB
    Doug Burger

    The University of Texas at Austin, United States

    4 publications · 2.3K citations

    4

    h-index

1–5 of 233

Venues

  1. IEEE Access

    3 publications · 184 citations

    3

    h-index

  2. IEEE Micro

    3 publications · 668 citations

    3

    h-index

  3. arXiv (Cornell University)

    Repository · 3 publications · 101 citations

    3

    h-index

  4. ACM SIGARCH Computer Architecture News

    2 publications · 271 citations

    2

    h-index

  5. IEEE Transactions on Computers

    2 publications · 69 citations

    2

    h-index

1–5