IEEE Transactions on Electron Devices · 2020 · 53 citations · 11 references
EngineeringComputer EngineeringField-programmable Gate ArraysParallel AlgorithmsParallel ComputingHardware AccelerationMemory DevicesMemory SystemsMemristive MaterialsParallel ArchitecturesConductanceMemory Circuit DesignMemristive Crossbar ArraysMemristive MemoryNeuromorphic DevicesNeuromorphic HardwareParallel EfficiencyResistive Random-access Memory
Resistive random access memory (RRAM) has been extensively studied as a promising candidate for neuromorphic computing. So far, high-precision multibit programming of RRAM for neuromorphic systems is done cell-by-cell, which can be very time-consuming. This brief demonstrates a row-by-row parallel program-verify scheme on a fabricated 160-Kb RRAM array using the incremental gate voltage programming (IGVP) method. Statistical analysis indicates that the optimal conductance tuning step size can accelerate the programming process and improve the success rate. Also, for the first time, the fundamental relations between programming success rate, critical path, and parallel efficiency for parallel program-verify methodology on the RRAM array are systematically studied. Moreover, a software-comparable recognition accuracy with only <; 0.3% accuracy loss is experimentally achieved for MNIST data set classification utilizing the proposed parallel program-verify scheme.
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