Design and Fabrication of Ion-Implanted Moat Etch Termination Resulting in 0.7 m$\Omega\cdot$ cm²/1500 V GaN Diodes

Abstract

The design space of ion-implanted moat etch termination in GaN p-n diodes is discussed in this study. Based on experimental data, the design window for ion-implanted moat etch termination has been carefully studied and optimized for vertical GaN p-n diodes grown on bulk GaN substrates. A high-performance diode with a breakdown voltage of 1500 V and a low specific on-state resistance of 0.7 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is demonstrated using the optimized edge termination based on moat etch and Mg ion implantation. The p-n diode shows a device figure-of-merit of 3.2 GW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . By using the proposed ion-implanted moat etch termination, GaN diodes with three different drift region designs approach the avalanche breakdown electric field, which indicates the efficacy of the proposed edge termination design and method.