Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

A Suggestion for a Fast Multiplier

Christopher S. Wallace · IEEE Transactions on Electronic Computers · 1964 · 1.8K citations

Engineering, Computer Engineering, Electrical Engineering +8

BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture

M. Mottaghi-Dastjerdi, Ali Afzali‐Kusha, Massoud Pedram · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009 · 57 citations

Engineering, Computer Engineering, Electrical Engineering +14

Low-power fixed-width array multipliers

Jinn‐Shyan Wang, Chien‐Nan Kuo, Tsung-Han Yang · 2004 · 35 citations

Engineering, Computer Engineering, Electrical Engineering +16

Design and FPGA implementation of optimized 32-bit Vedic multiplier and square architectures

Richa Sharma, M. Kaur, Gurmohan Singh · 2015 · 33 citations

Engineering, Computer Engineering, Computer Science +15

Low Power Square and Cube Architectures Using Vedic Sutras

Vaijyanath Kunchigi, Linganagouda Kulkarni, Subhash Kulkarni · 2014 · 21 citations

Engineering, Computer Engineering, Computer Science +17