A Suggestion for a Fast Multiplier

TLDR

Large‑scale scientific computers could be made more cost‑effective by investing more in hardware for multiplication and division. The paper proposes a fast multiplier that produces the product of two numbers in a single gating step and outlines a rapid square‑root process. The multiplier is implemented with straightforward diode‑transistor combinational logic that yields products in under 1 µs and quotients in 3 µs. Component counts indicate the unit would cost roughly 10 % of a modern large‑scale computer.

Abstract

It is suggested that the economics of present large-scale scientific computers could benefit from a greater investment in hardware to mechanize multiplication and division than is now common. As a move in this direction, a design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step. Using straightforward diode-transistor logic, it appears presently possible to obtain products in under 1, μsec, and quotients in 3 μsec. A rapid square-root process is also outlined. Approximate component counts are given for the proposed design, and it is found that the cost of the unit would be about 10 per cent of the cost of a modern large-scale computer.