A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET

Abstract

This 56Gb/s PAM-4 transceiver leverages the high logic density provided by the 7nm FinFET technology through rigorous application of digital design styles: An All-Digital PLL and SST transmitter are combined with a 28GS/s 8b ADC and DSP receiver, with the analog signal processing limited to a two stage front-end. The receiver achieves a raw 1e-7 BER with a-33dB insertion loss channel while consuming 500mW, including the 20-tap FFE and 1-tap DFE equipped DSP section.