2019 · 12 citations · 4 references
EngineeringDigital DesignElectrical EngineeringAnalog ElectronicsDigital CommunicationSemiconductor DevicesDigital Integrated Circuit DesignDigital Logic DesignDigital Signal ProcessingLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationAnalog Signal ProcessingAnalog-to-digital Converter DesignCmos Logic DesignComplementary Metal-oxide-semiconductor LogicFin Field-effect TransistorsTransceiver ArchitecturesTransceiver DesignTransmitter Design
This 56Gb/s PAM-4 transceiver leverages the high logic density provided by the 7nm FinFET technology through rigorous application of digital design styles: An All-Digital PLL and SST transmitter are combined with a 28GS/s 8b ADC and DSP receiver, with the analog signal processing limited to a two stage front-end. The receiver achieves a raw 1e-7 BER with a-33dB insertion loss channel while consuming 500mW, including the 20-tap FFE and 1-tap DFE equipped DSP section.
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