A Highly Reliable SRAM PUF with a Capacitive Preselection Mechanism and pre-ECC BER of 7.4E-10

Abstract

An SRAM PUF with an internal error reduction mechanism is presented. A capacitive preselection test identifies potentially unstable cells with insufficient mismatch. The test can be accomplished in one VDD / temperature corner. An implementation in TSMC 65nm technology disqualified all the unstable cells (19.7%) in 14 800-bit arrays. The test has no impact on the randomness of the PUF and negligible impact on area. A highly competitive pre-ECC BER of 7.4E-10 and an energy consumption of 16fJ/bit were achieved.