Analysis the complex tradeoff among E<sub>on</sub>-V<sub>CEsat</sub>-SCSOA and EMI noise through the single chip evaluation method

Koichi Nishi, Atsushi Narazaki

2019 · 17 citations · 7 references

Concepts

Abstract

As a compensation for the superior V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEsat</sub> , Carrier Stored Trench gate Bipolar Transistor (CSTBT™) has the more complex tradeoff among E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEsat</sub> -SCSOA and EMI noise compared to IGBT. EMI noise evaluation is known to need special facilities such as a shield room and antenna detector, which deteriorates an evaluation efficiency and consistency. We found that EMI noise can be indirectly but simply and accurately evaluated by using the surge current under small current turn-on of single-chip IGBTs without any EMI shield facilities. By using this method, maintaining the CSTBT's better tradeoff among E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEsat</sub> -SCSOA, we have succeeded to reduce the EMI noise by decreasing Carrier Stored Layer doping concentration and/or gate-collector capacitance while adjusting channel density.

References

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