Excellent Device Performance of Sub‐5‐nm Monolayer Tellurene Transistors

Abstract

Abstract The merging 2D semiconductor tellurene (2D Group‐VI tellurium) is a possible channel candidate for post‐silicon field‐effect transistor (FETs) due to its high carrier mobility, high drive current, and excellent air stability. The performance limits of sub‐5‐nm ML tellurene metal‐oxide‐semiconductor FETs (MOSFETs) are explored by employing exact ab initio quantum transport simulations. An optimized p‐type ML tellurene MOSFET meets both the high performance (along both the armchair and the zigzag directions) and the low power (along the armchair direction) requirements of the International Technology Roadmap for Semiconductors (ITRS) at a gate length of 4 nm with a negative capacity dielectric. Hence, choosing ML tellurene as the channel material provides a novel route to continue the Moore's law to 4 nm.