Study on Warpage and Reliability of Fan-Out Interposer Technology

Abstract

The fan-out interposer (FOI) technology with fine pitch is demonstrated and presented for heterogeneous integration as a cost-effective and enabling technology. The co-design modeling methodology is established for the FOI technology, including wafer process-induced warpage, package assembly warpage, and board-level solder joint reliability to optimize the structure design, wafer process, assembly process, and material selection. Through the wafer warpage modeling, desirable glass carrier, photodielectric, and molding compound materials and interposer structure are suggested to reduce the wafer warpage. Effect of stiffener on assembly induced package warpage is simulated and studied. Board-level solder joint reliability is investigated and optimized based on the simulation results. The optimized materials and the structure design are determined based on the co-design modeling and simulation results to achieve the successful FOI wafer fabrication, assembly process, and board-level reliability for extreme large package with FOI.