A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS

Abstract

This paper presents a 14-bit radiation- and metastability-tolerant two-step split successive-approximation register (SAR) analog-to-digital converter (ADC) that achieves a 78.5-dB peak signal-to-noise-and-distortion ratio (SNDR) and a 103-dB peak spurious-free dynamic range (SFDR) at 35 MS/s. The prototype operates up to 75 MS/s with less than 25-mW power consumption. To tolerate errors originating from radiations and/or metastability, multiple redundancy techniques are implemented hierarchically from the system level to the circuit level. At the system level, the deployment of the split architecture plus a few additional error detection techniques not only identify but also correct the errors, leading to a p to p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> error rate reduction. These detection techniques include a residue over- and under (OU)-flow detection using the second-stage digital codes, an extra bit (EB)-cycle error detection with LSB repeating using a larger digital-to-analog converter (DAC) capacitor, and a parity bit (PB) error detection for on-the-fly SAR data latch protection. Sub-radix-2 DAC and reference voltage scaling also create circuit-level intra- and inter-stage redundancy, further improving the robustness of the conversion process. Preamplifier sharing and offset digital calibration alleviate the offset problem between the residue amplifier (RA) and the first-stage comparator. Two reference buffers are implemented on chip with a 1.8-V supply. Fabricated in a 65-nm CMOS process, the ADC core occupies an active area of 0.342 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .