IEEE Transactions on Circuits & Systems II Express Briefs · 2018 · 13 citations · 3 references
Power ConsumptionElectrical EngineeringBidirectional Shift-registerEngineeringVlsi DesignClock SignalsMixed-signal Integrated CircuitComputer EngineeringComputer ArchitectureDigital Circuit DesignMicroelectronicsBeyond Cmos
This brief proposes an area-efficient bidirectional shift-register using bidirectional pulsed-latches. The proposed bidirectional shift-register reduces the area and power consumption by replacing master-slave flip-flops and 2-to-1 multiplexers with the proposed bidirectional pulsed-latches and non-overlap delayed pulsed clock signals, and by using sub shift-registers and extra temporary storage latches. A 256-bit bidirectional shift-register was fabricated using a 65 nm CMOS process. Its area was 1943 μm2 and its power consumption is 200 μW at a 100 MHz clock frequency with VDD = 1.2 V. It reduces area by 39.2% and power consumption by 19.4% compared to the conventional bidirectional shift-register.
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