Design and Analysis of Wallace Tree Multiplier for CMOS and CPL Logic

Abstract

In this paper we have designed and analysed Wallace Tree Multiplier for CMOS and CPL Logics. CPL Logic is low power logic. This paper aims at comparing the area, power and delay of Wallace Tree Multiplier for CMOS and CPL Logics. The design is implemented using HSPICE for 180nm Technology. Wallace Tree Multiplier was designed for 8-bit and 16-bit using 3:2,4:2 and 5:2 compressors.