Concepedia

S. Nagaraj

SN

Statistics

Publications

9

Citations

144

H-Index

9

Active since

2017

Affiliations

Chaitanya Bharathi Institute of Technology(Current)

S. Nagaraj is an author at Chaitanya Bharathi Institute of Technology specializing in engineering, microelectronics, and multiplier design.

Publications per year

2017–2023

9

Publications

9

Modified High Speed 32-bit Vedic Multiplier Design and Implementation

M. Bala Murugesh, S. Nagaraj, J. Jayasree et al. · 2020 International Conference on Electronics and Sustainable Communication Systems (ICESC) · 2020 · 36 citations

Engineering, Computer Engineering, Computer Science +12

Design and analysis of high speed and low area vedic multiplier using carry select adder

D Yaswanth, S. Nagaraj, R.Vishnu Vijeth · 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE) · 2020 · 22 citations

Engineering, Computer Engineering, Electrical Engineering +13

Analysis of different Adders using CMOS, CPL and DPL logic

S. Nagaraj, Gajulapalli Mahitha Reddy, S. Aruna Mastani · 2017 · 17 citations

Engineering, Computer Engineering, Electrical Engineering +17

Design and Analysis of Wallace Tree Multiplier for CMOS and CPL Logic

S. Nagaraj, K. Thyagarajan, D. Srihari et al. · 2018 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +15

Analysis of 32-Bit Multiply and Accumulate unit (MAC) using Vedic Multiplier

K. Lilly, S. Nagaraj, B. Manvitha et al. · 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE) · 2020 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +14

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