34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms

Abstract

A 9,296μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> DEFLATE accelerator targeted for firmware decompression in battery-constrained IoT platforms is fabricated in 14nm tri-gate CMOS, and operates over a wide supply range of 210-900m V. Dual-ALU block-adaptive Huffman decoder enables simultaneous evaluation of a pair of code-lengths with opportunistic skipping of non-existent symbols improving throughput by 34% to 1.65Gb/s at 750mV, 25°C, while in-line literal packing and fenced-record generation achieves 63% memory bandwidth reduction for LZ77 reconstruction. Absence of register file and CAM circuits result in a fully-synthesizable implementation enabling ultra-low voltage operation with peak energy-efficiency of 1.56Tbps/W and 34.4Mbps throughput at 22μW total power consumption measured at 310mV.