Fan-Out Wafer-Level Packaging for Heterogeneous Integration

Abstract

The design, materials, process, fabrication, and reliability of a heterogeneous integration of 4 chips and 4 capacitors by a FOWLP (fan-out wafer-level packaging) method are investigated in this study. Emphasis is placed on the application of a new assembly process for fabricating the RDLs (redistribution layers) of the FOWLP. Reliability assessments such as the drop test are also performed.