IEEE Transactions on Circuits & Systems II Express Briefs · 2018 · 20 citations · 15 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsClock ManagementCmos Circuit DesignDynamic Power ReductionJitter AnalysisOscillatorsPower OptimizationClock GenerationClock Network Power ReductionClock Power OptimizationComparator DesignFrequency StabilityJitterOn-chip Clock Power OptimizationRelaxation Oscillators
This brief presents a low-power low-jitter relaxation oscillator for on-chip low-frequency clock generation. A dynamic common-gate comparator is proposed to reduce the power, combined with a slope boosting technique to reduce the period jitter. A peak-detecting feedback loop is implemented to maintain frequency stability over temperature variations. The oscillator achieves 0.025% period jitter and 70 ppm/°C temperature coefficient while consuming 1.36 μW at 364 kHz with a 1.2-V supply.
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Noise in relaxation oscillators
A.A. Abidi, Ralf Meyer · IEEE Journal of Solid-State Circuits · 1983 · 227 citations