A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS

Abstract

PAM-4 modulation paired with forward error correction schemes has been introduced in recent wireline communication standards operating up to 56Gb/s per-lane. PAM-4 enables a more efficient use of the available link bandwidth but, compared to NRZ, design of low-power transceivers entails new challenges. Transmitters must deliver high swing with wide bandwidth and high linearity [1-3]. The multilevel signal suffers from heightened sensitivity to channel loss and reflections, because transitions between adjacent levels are impaired from ISI generated by 3x larger pk-to-pk transitions [4]. As a result, enhanced equalization accuracy is mandatory before symbol detection.