Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs

Abstract

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for next generation computing systems. However, with increasing process variation and decreasing supply voltage, a big design challenge of embedded STT-MRAMs is to guarantee negligible read disturbance and high yield. To deal with the read reliability challenge, an offset compensated, high-speed sense amplifier (OCHS-SA) is proposed, which is based on combining the sensing circuit and latch sense amplifier (SA). The proposed OCHS-SA scheme offers four major advantages including offset compensation, high sensing margin (SM), strong positive feedback, and latching feature with compact area. Simulation results show that the SM is at least 700 mV at VDD = 1 V with a sensing time of 3.5 ns, and it provides the lowest energy consumption/area overhead over compared SAs.