A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET

Abstract

ADC-based transceivers having up to 8 bits of resolution have been reported for PAM-4 links above 50Gb/s [1,2], although fewer bits are sufficient and offer lower power for short reach (SR) channels. To further reduce the power consumption of ADC-based wireline transceivers, non-uniform quantization has been explored [3,4] using performance metrics for the complete link, such as bit-error rate (BER), to optimize the quantizer thresholds. Both [3,4] are PAM-2 (NRZ) receivers, demonstrating non-uniform quantization specifically for a decision feedback equalizer (DFE) at 10Gb/s and a feedforward equalizer (FFE) at 4Gb/s respectively. An LMS algorithm in [4] adjusts the threshold levels requiring fine-tuning (8b resolution). This paper presents a 64Gb/s PAM-4 transceiver utilizing an ADC-based receiver (RX), with an analog front-end (AFE) based on a 6b, 1b folding, flash ADC with adaptive threshold levels. A fast greedy-search algorithm is used to choose the optimal quantizer thresholds for minimum BER over a given channel. This provides a near-optimal way of power-scaling the ADC when the channel loss doesn't require the ADC's full resolution. The optimization can work in the background for any equalizer structure, does not place additional requirements on the ADC design, and never diverges, unlike LMS-based approaches [4].