2018 · 81 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringDigital CommunicationPhotonicsSystem-on-chip DesignCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignOptical Communication SystemsAnalog-to-digital Converter DesignData Converter ArchitectureData Converter DesignDigital Signal Processing Block ArchitectureDigital Signal Processing BlocksEqualizationTransceiver ArchitecturesTransceiver Design
The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards in the 100Gb/s+ regime [1]. Although these standards are still in the definition phase they will rely on multi-level signaling such as PAM-4 along with an increasing amount of digital signal processing. In the foreseeable future, a high-performance TX will consist of a CMOS DSP frontend followed by a high sampling rate data converter [2,3], whose design remains a significant challenge. This paper presents a 112Gb/s PAM-4 SST Tx that is based on a quarter-rate 56GS/s 8b SST DAC along with a digital 8-tap FIR filter for channel equalization.
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3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS
Jihwan Kim, Ajay Balankutty, Amr Elshazly et al. · 2015 · 102 citations
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory
Yuriy Greshishchev, D. Pollex, Shing-Chi Wang et al. · 2011 · 59 citations