28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET

Lukas Kull, Danny Luu, Christian Menolfi, +8

Conversion SpeedPipelined-sar AdcData ConverterMixed-signal Integrated CircuitAnalog Design +5

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

İlter Özkaya, Alessandro Cevrero, Pier Andrea Francese, +14

IEEE Journal of Solid-State Circuits

EngineeringOptical Transmission SystemIntegrated CircuitsOptical AmplifierOptical Properties +15

A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

Lukas Kull, Danny Luu, Christian Menolfi, +7

IEEE Journal of Solid-State Circuits

Differential Capacitive Dac14-Nm Cmos FinfetData ConverterMixed-signal Integrated CircuitAnalog Design +5

A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

Christian Menolfi, Thomas Toifl, Matthias Bräendli, +7

Pam-4 Sst TxElectrical EngineeringEngineeringVlsi DesignSst Dac +13

6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET

Alessandro Cevrero, İlter Özkaya, Pier Andrea Francese, +8

Power ConsumptionWireless CommunicationsElectrical EngineeringPam-4 RxEngineering +10

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Gain Kim, Marcel Kossel, Alessandro Cevrero, +12

IEEE Journal of Solid-State Circuits

Electrical EngineeringEngineeringPrototype Rx ChipData ConverterMixed-signal Integrated Circuit +8

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

Jonathan E. Proesel, Zeynep Toprak-Deniz, Alessandro Cevrero, +9

IEEE Journal of Solid-State Circuits

Optical MaterialsEngineeringIntegrated CircuitsProgrammable PhotonicsOptical Computing +14

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese, +9

IEEE Journal of Solid-State Circuits

Far-end Crosstalk CancellationRx MacroEngineeringDecision-feedback Crosstalk CompensationMixed-signal Integrated Circuit +5

A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET

Lukas Kull, Danny Luu, Christian Menolfi, +7

Engineering24-To-72gs/s 8BData ConverterOptical Communication StandardsAnalog Design +9

Power-gated MOS current mode logic (PG-MCML)

Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, +3

Low-power ElectronicsHardware SecurityElectrical EngineeringPower-aware ComputingEngineering +10