A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

Abstract

A 24-72-GS/s 8-b time-interleaved analog-to-digital converter (ADC) is presented which exceeds 39-dB SNDR at low input frequency and 30-dB SNDR at Nyquist. High SNDR at Nyquist is achieved by 16 parallel sampling switches driven by short clock pulses. Clock-pulse edges can be shifted digitally to reduce the impact of timing mismatch. A total of 64 asynchronous 8-b successive approximation (SAR) ADCs at low supply voltage convert sampled voltages. The SAR ADCs use a differential capacitive DAC, one comparator per decision, and include a reference voltage DAC and buffer. The ADC consumes 2.0 pJ/conversion at 48 GS/s and 3.3 pJ/conversion at 72 GS/s and is implemented in 14-nm CMOS FinFET on 0.15 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .