Demonstrating >1.4 kV OG-FET performance with a novel double field-plated geometry and the successful scaling of large-area devices

Abstract

A normally off (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> = 4.7 V) vertical GaN OG-FET with a 10 nm UID-GaN channel interlayer and a 50 nm in-situ Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric has been successfully demonstrated and scaled for higher current operation. By using a novel double field-plated structure for mitigating peak electric field, a high off-state breakdown voltage over 1.4 kV was achieved with a low specific on-state resistance (RON, SP) of 2.2 mΩ.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The MOCVD regrown 10 nm GaN channel interlayer enabled a channel resistance lower than 10 Qmm and an average channel electron mobility of 185 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs. The fabricated large-area transistor with a total area of 400 μm × 500 μm offered a breakdown voltage of 900 V and an on-state resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) of 4.1 Q. Results indicate the potential of vertical GaN OG-FETs for over kV range of power electronics applications.