Impact of aggressive fin width scaling on FinFET device characteristics

Abstract

Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This paper studies the benefits, trade-offs and limitations of aggressive fin width (W) scaling on logic and SRAM device characteristics. TCAD analysis is used to understand the impact of gate length (Lg)scaling along with fin width scaling to optimize AC performance. In this paper, W was scaled from 8nm to 1.6nm. It was found that there is a critical fin width (Wc)at ~4nm. In the W>Wc region, due to better electrostatics from narrower fin, drain-induced barrier lowering (DIBL), DC performance and SRAM Vt mismatch (Vtmm) were improved. As W was scaled down further to W<;Wc region, DIBL benefit was reduced and DC performance degraded rapidly from drivability loss. Additionally, Vtmm improvement saturated from increased sensitivity to fin bottom punch-through. As W is reduced, TCAD simulations show reduced inversion carrier density from quantum confinement, and mobility degradation from stress relaxation (PFETs) or phonon scattering and surface roughness scattering (both NFETs and PFETs). From TCAD simulations DIBL is much less sensitive to gate length scaling for narrower fins, which can be leveraged to improve Ceff and AC performance by Lg reduction. A 16% improvement in AC performance is predicted when Lg is reduced by 6nm for FinFETs as W is scaled from 8nm to W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">~</sup> 4nm.