2017 · 27 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignOptoelectronicsPhotonicsClock ManagementDigital Signal ProcessingLow-noise Circuit DesignOptical Communication SystemsOptical InterconnectsOptical Signal ProcessingClock GenerationClock JitterClock RecoveryHigh-speed InterconnectsOptical SamplingOptical TransceiversPower Conversion EfficiencyPower Efficiency
A quarter-rate 51Gb/s PAM4 CDR with decoded dual-NRZ outputs is presented for 400GbE optical transceivers. A baud-rate data-only sampling PD with zero-crossing integrating front-end is proposed to minimize the clock generation and distribution overhead, as well as improving the noise resilience under PAM4 low-SNR inputs. Measurement results show the CDR features 1.08ps RMS clock jitter, 3.4×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> PAM4 data recovery BER, and 6.27pJ/bit power efficiency.
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A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology
Reza Navid, E-Hung Chen, Masum Hossain et al. · IEEE Journal of Solid-State Circuits · 2014 · 85 citations