An improved SiC MOSFET-gate driver integrated power module with ultra low stray inductances

Abstract

An improved SiC MOSFET-gate driver integrated half-bridge module with folded layout using direct bonded copper (DBC) substrate is designed, fabricated, and tested. The bottom layer of the DBC is used as part of the power loop to achieve major reduction in the loop stray inductance. Due to the low parasitic inductance and capacitance, the gate resistor is chosen as zero to reduce the switching loss and the EMI performance is improved under high switching speed. Simulation and experimental results show the better switching performance comparing with traditional one-layer module.