Implementation of power efficient 8-bit reversible linear feedback shift register for BIST

Abstract

Built-in Self Test (BIST) is more appropriate for testing any VLSI circuits as it provides a larger range for low power applications. Test pattern generator is the vital module in BIST. Linear Feedback Shift Registers (LFSR) is broadly used in BIST for generating test vectors as it produces highly random test pattern. This paper mainly aims at design and implementation of power efficient LFSR using reversible logic for low power applications. Pareek Gate is used to implement reversible D Flip Flop (DFF). 8 bit reversible LFSR is implemented using 8 DFFs, 8 Feynman Gates (FG) and 3 Double Feynman Gates (DFG). It is found from the analysis that, the proposed approach of designing reversible LFSR reduces the power by 10% when compared to conventional design. Thus the proposed design can be used for designing BIST in low power applications.