Evaluation of the hardwired sequence control system generated by high-level synthesis

Abstract

This study presents the application of the commercial High Level Synthesis (HLS) to a hardwired control application with quantitative comparison to the traditional approach that uses logic synthesis with HDL. Though the derived circuits from HLS are comparable to that of logic synthesis, the design trade-offs in HLS are difficult to control. This study also presents the design and evaluation of the whole system of hardwired control with a Xilinx Zynq-7000 FPGA platform. From our experiments, two performance bottlenecks were identified: the RAM for memory elements that serializes the read/write accesses, and data transfer time via the peripheral bus. According to our results, the sole hardwired control was 10 times faster than the original software, while the overall performance was 4 to 50 times worse than the original software. The use of flipflops and dedicated I/O pins are necessary for high-performance systems.