Peripheral Bus Architecture
Peripheral Bus Architecture is a systematic framework that defines the structural and functional organization of communication pathways between a microcontroller and its peripheral devices, distinguishing itself by specifying protocols, data width, timing mechanisms, and addressing schemes to enable synchronized and efficient data exchange within embedded systems.
42
Publications
1.1K
Citations
121
Authors
41
Institutions
Publications per year
2017–2026
6
42
Gadi Kaplan · IEEE Spectrum · 1995 · 72 citations
AMULET3i-an asynchronous system-on-chip
Jim Garside, W.J. Bainbridge, Andrew Bardsley et al. · 2002 · 56 citations
Engineering, Computer Engineering, Electrical Engineering +12
1–5 of 42
121
2
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2
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2
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National Institute of Information and Communications Technology, Japan
2 publications · 56 citations
2
h-index
National Institute of Advanced Industrial Science and Technology, Japan
2 publications · 56 citations
2
h-index
1–5 of 121
41

University of Manchester
Manchester, United Kingdom
2 h-index
12 publications
638 citations
Amity University
Noida, India
2 h-index
6 publications
96 citations

Nara Institute of Science and Technology
Ikoma, Japan
2 h-index
8 publications
224 citations
Astronomical Observatory
Belgrade, Serbia
1 h-index
4 publications
44 citations
Eskişehir City Hospital
Eskişehir, Turkey
1 h-index
1 publications
34 citations
Institut de Microelectrònica de Barcelona
Cerdanyola del Vallès, Spain
1 h-index
1 publications
22 citations
Advanced Numerical Research and Analysis Group
Hyderabad, India
1 h-index
1 publications
17 citations
University of California, Santa Barbara
Santa Barbara, United States
1 h-index
3 publications
102 citations
1–8 of 41
1 publications · 15 citations
1
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1 publications · 44 citations
1
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1 publications · 22 citations
1
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1 publications · 34 citations
1
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1 publications · 20 citations
1
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1–5