Peripheral Bus Architecture

Peripheral Bus Architecture is a systematic framework that defines the structural and functional organization of communication pathways between a microcontroller and its peripheral devices, distinguishing itself by specifying protocols, data width, timing mechanisms, and addressing schemes to enable synchronized and efficient data exchange within embedded systems.

42

Publications

1.1K

Citations

121

Authors

41

Institutions

Publications per year

2017–2026

6

Authors

121

  1. KR
    Kiran Rawat

    Amity University, India

    2 publications · 32 citations

    2

    h-index

  2. KF
    Kazutoshi Fujikawa

    Nara Institute of Science and Technology, Japan

    2 publications · 56 citations

    2

    h-index

  3. KS
    Kanika Sahni

    Amity University, India

    2 publications · 32 citations

    2

    h-index

  4. EK
    Eiji Kawai

    National Institute of Information and Communications Technology, Japan

    2 publications · 56 citations

    2

    h-index

  5. TH
    Takahiro Hirofuchi

    National Institute of Advanced Industrial Science and Technology, Japan

    2 publications · 56 citations

    2

    h-index

1–5 of 121

Venues

  1. 1

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  2. Journal of Computer Assisted Learning

    1 publications · 44 citations

    1

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  3. International Journal of Technology

    1 publications · 22 citations

    1

    h-index

  4. 1

    h-index

  5. IEEE Journal of Solid-State Circuits

    1 publications · 20 citations

    1

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1–5