Răzvan Nane - Concepedia

Author

Răzvan Nane

Delft University of Technology ORCID

Also Known As

Nane, R., Nane, Razvan, R. Nane, Razvan Nane, Rustad, Alf Birger, Răzvan Nane

Publications

842

Citations

H-Index

Concepts

All Affiliations

Delft University of Technology

About

Răzvan Nane is an author at Delft University of Technology specializing in computer engineering, computer architecture, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	781
2	Computer Engineering	9	9	781
3	Computer Science	8	8	764
4	Electrical Engineering	3	3	80
5	Social Sciences	1	1	14

Răzvan Nane

Publications

781

Citations

H-Index

Page 1

	Year	Citations
A Survey and Evaluation of FPGA High-Level Synthesis Tools Răzvan Nane, Vlad-Mihai Sima, Christian Pilato, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringHardware Verification LanguageComputer ArchitectureSystem-level DesignSystem Synthesis	2015	518
DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler Răzvan Nane, Vlad-Mihai Sima, Bryan Olivier, EngineeringHardware Verification LanguageCompiler TechnologyModular CompilerComputer Architecture	2012	82
OpenQL: A Portable Quantum Programming Framework for Quantum Accelerators N. Khammassi, Imran Ashraf, J. van Someren, ACM Journal on Emerging Technologies in Computing Systems Quantum CompilersQuantum ScienceEngineeringQuantum ComputingQuantum Optimization Algorithm	2021	53
On the Implementation of Computation-in-Memory Parallel Adder Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, IEEE Transactions on Very Large Scale Integration (VLSI) Systems EngineeringComputer ArchitectureComputation-in-memory Parallel AdderParallel ImplementationHardware Security	2017	34
Computation-in-memory based parallel adder Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, EngineeringComputer ArchitectureParallel ImplementationParallel AdderMulti-channel Memory Architecture	2015	23
Parallel matrix multiplication on memristor-based computation-in-memory architecture Adib Haron, Jintao Yu, Răzvan Nane, Hardware SecurityElectrical EngineeringMemory-processor Communication BottleneckEngineeringMemristor-based Computation-in-memory Architecture	2016	23
Controlling a complete hardware synthesis toolchain with LARA aspects João M. P. Cardoso, Tiago Carvalho, José G. F. Coutinho, Microprocessors and Microsystems EngineeringHardware Verification LanguageComputer EngineeringFormal MethodsSystems Engineering	2013	17
Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA Bjorn Sigurbergsson, Tom Hogervorst, Tong Qiu, Hardware SecurityMassively-parallel ComputingArray ComputingEngineeringHardware Acceleration	2019	17
High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain Răzvan Nane, Vlad-Mihai Sima, Cuong Pham‐Quoc, EngineeringHardware Verification LanguageElectronic Design AutomationComputer ArchitectureSoftware Engineering	2014	14

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