DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler

TLDR

Hardware design automation has advanced by extracting parallelism from applications, yet existing tools are either domain‑specific or restrict the input language. This work introduces DWARV 2.0, a compiler that accepts arbitrary C code and produces synthesizable VHDL for any application domain. DWARV 2.0 is built on the CoSy compiler framework, enabling a highly modular architecture where standard or custom optimizations can be integrated easily. Experimental validation shows that DWARV 2.0 achieves speed‑ups of up to 4.41× compared with a leading state‑of‑the‑art hardware compiler.

Abstract

In the last decade, a considerable amount of effort was spent on raising the implementation level of hardware systems by automatically extracting the parallelism from input applications and using tools to generate Hardware/Software co-design solutions. However, the tools developed thus far either focus on particular application domains or they impose severe restrictions on the input language. In this paper, we present the DWARV 2.0 compiler that accepts general C-code as input and generates synthesizable VHDL for unrestricted application domains. Dissimilar to previous hardware compilers, this implementation is based on CoSy compiler framework. This allowed us to build a highly modular compiler in which standard or custom optimizations can be easily integrated. Validation experiments showed speed-ups of up to 4.41× when comparing against another state of the art hardware compiler.