Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors

Abstract

This work proposes a Sum of Absolute Transformed Differences (SATD) architecture based on multiple sizes Hadamard Transforms (HTs) and adder compressors, where the smallest HTs are reused for the implementation of the largest ones. A new adder/subtractor compressor is proposed and used to implement additions and subtractions of the HT module, while conventional 4-2 and 8-2 adder compressors are used to implement the Sum of Absolute Values (SAV) module. Synthesis results for 45 nm technology show that SATD architecture with the proposed adder/subtractor compressors reduces power dissipation in 10%, on average, when compared with SATD architecture using the macrofunction adder operator from the tool.