1c:I[419806,["/_next/static/chunks/bb923814e1f4d2e9.js","/_next/static/chunks/dd3ee9f5b7716ca6.js","/_next/static/chunks/4204a0ae82542ca8.js","/_next/static/chunks/1270dead247da766.js","/_next/static/chunks/6e1aa89a642f40be.js","/_next/static/chunks/2d7aa753e81324a8.js","/_next/static/chunks/8ffd0b71567920d8.js","/_next/static/chunks/67ea6dfd21f16c5f.js","/_next/static/chunks/24eb4379f68013fd.js","/_next/static/chunks/b8cd775ffdf935bd.js","/_next/static/chunks/983103cd9eb7b428.js","/_next/static/chunks/263f2cdcb9aa2341.js","/_next/static/chunks/294b9525248c8e5f.js"],"default"] 1d:T506,The multilevel capability of metal oxide resistive switching memory was explored for the potential use as a single-element electronic synapse device. TiN/HfO x /AlO x / Pt resistive switching cells were fabricated. Multilevel resistance states were obtained by varying the programming voltage amplitudes during the pulse cycling. The cell conductance could be continuously increased or decreased from cycle to cycle, and about 10 ⁵ endurance cycles were obtained. Nominal energy consumption per operation is in the subpicojoule range with a maximum measured value of 6 pJ. This low energy consumption is attractive for the large-scale hardware implementation of neuromorphic computing and brain simulation. The property of gradual resistance change by pulse amplitudes was exploited to demonstrate the spike-timing-dependent plasticity learning rule, suggesting that metal oxide memory can potentially be used as an electronic synapse device for the emerging neuromorphic computation system.1e:T48a,Vector-matrix multiplication dominates the computation time and energy for many workloads, particularly neural network algorithms and linear transforms (e.g, the Discrete Fourier Transform). Utilizing the natural current accumulation feature of memristor crossbar, we developed the Dot-Product Engine (DPE) as a high density, high power efficiency accelerator for approximate matrix-vector multiplication. We firstly invented a conversion algorithm to map arbitrary matrix values appropriately to memristor conductances in a realistic crossbar array, accounting for device physics and circuit issues to reduce computational errors. The accurate device resistance programming in large arrays is enabled by close-loop pulse tuning and access transistors. To validate our approach, we simulated and benchmarked one of the state-of-the-art neural networks for pattern recognition on the DPEs. The result shows no accuracy degradation compared to software approach (99 % pattern recognition accuracy for MNIST data set) with only 4 Bit DAC/ADC requirement, while the DPE can achieve a speed-efficiency product of 1,000× to 10,000× compared to a custom digital ASIC.1f:T464,We report on world's smallest HfO ₂ -based Resistive RAM (RRAM) cell to date, featuring a novel Hf/HfO _x resistive element stack, with an area of less than 10×10 nm ² , fast ns-range on/off switching times at low-voltages and with a switching energy per bit of <;0.1pJ. With excellent endurance of more than 5.10 ⁷ cycles, large on/off verified-window (>;50), no closure of the on/off window after 30hrs/200C and failure-free device operation after 30hrs/250C thermal stress, the major device-level nonvolatile memory requirements are met. Furthermore, we clarify the impact of film crystallinity on cell operation from a scalability v

	Year	Citations

References