Throughput enhancement strategy of maskless electron beam direct writing for logic device

Abstract

A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P and R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.