Impact of technology scaling on the input and output features of RF-MOSFETs: effects and modeling

Abstract

In this paper, the effect of the gate, channel, and substrate resistances on the MOSFET's input and output ports has been investigated when the CMOS technology is scaled from the 0.18 /spl mu/m to the sub-100 nm regime by analyzing S-parameter measurements. Results showed new features to be considered in the modeling of the input port of sub-100 nm devices, while the output port remains almost insensitive to technology scaling. Additionally, an enhanced model for the gate electrode impedance and a novel substrate resistance extraction technique are proposed to study the device's characteristics at RF.