2007 · 21 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDynamic Power ReductionHigh-frequency Power ConversionHigh-frequency Semiconductor DevicesDuty Cycle AnalysisDuty Cycle ControlDuty Cycle CorrectionHigh-frequency ElectronicsHigh-frequency OperationPower ConsumptionUltra-low-power Cmos
A duty cycle corrector based on pulse shrinking/ stretching mechanism is presented. The proposed DCC has been fabricated in a TSMC 0.35μm standard CMOS process. An input duty cycle range of 30%˜70% is achieved. The duty cycle error is within ±1.0% for the widest frequency operation range of 3MHz~660MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 x 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the power consumption is 1.1mW at 550 MHz.
9
An all-digital 50% duty-cycle corrector
Yiming Wang, Jinn‐Shyan Wang · 2004 · 52 citations
A CMOS 50% duty cycle repeater using complementary phase blending
Kazuyuki Nakamura, M. Fukaishi, Y. Hirota et al. · 2002 · 51 citations
Engineering, Computer Engineering, Electrical Engineering +14