Electronics Letters · 2003 · 32 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSystem-on-chip DesignClock ManagementCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsMixed-signal Integrated Circuit DesignRadio-frequency Integrated CircuitsCmos Analog Integrated CircuitsCmos Logic CircuitsCmos Radio-frequency CircuitsDuty Cycle ControlDuty Cycle CorrectionRf Cmos DesignVoltage Reference Design
A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations. The output duty cycle is adjusted to 50±0.25% throughout the input duty cycle range from 20% to 80% at the frequency of 1.25 GHz. 0.18 µm CMOS technology is used in this work.
3
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM
T.H. Lee, Kevin Donnelly, J. Ho et al. · IEEE Journal of Solid-State Circuits · 1994 · 178 citations
Engineering, Computer Engineering, Electrical Engineering +17