Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs

Abstract

Demonstrated double-gate devices with excellent drive current and short-channel-effect control. The double-gate devices exhibit ideal linear, sub-threshold slope of 60 mV/dec and better than ideal saturated sub-threshold slope of 55 mV/dec. The effective mobility in all device structures follows the universal mobility curve. The symmetric double-gate offers 20% mobility enhancement over a GP device at 1.0 V gate over-drive. Because the double-gate can be operated at a much lower effective-field, substantial mobility enhancement (>2X) over scaled bulk CMOS can be achieved. For the first time, DC operation of double-gate CMOS inverters are demonstrated down to Vdd=0.3 V.