A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO/sub 3/ and RIE patterned RuO/sub 2/TiN storage nodes

Abstract

A new stacked capacitor technology with high permittivity ECR MOCVD SrTiO/sub 3/ films on 1 Gbit compatible RuO/sub 2/TiN storage nodes was developed for Gigabit-scale DRAMs. A cell capacitance of 25 fF and leakage current density of 8/spl times/10/sup -7/ A/cm/sup 2/ can be achieved with this capacitor technology, using 0.5 /spl mu/m high stacked storage electrodes in a 0.125 /spl mu/m/sup 2/ capacitor area. Fine storage RuO/sub 2/TiN electrodes were patterned down to 0.2 /spl mu/m by electron beam lithography and RIE using an O/sub 2/-based etching mixture. A new low temperature ECR MOCVD technique was also developed to prepare highly reliable SrTiO/sub 3/ films to be used on the storage electrode sidewalls.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>