A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

Abstract

Results are presented for a novel trench capacitor DRAM cell using a vertical access transistor along the storage trench sidewall which effectively decouples the gate length from the lithographic groundrule. A unique feature of this cell is the vertical access transistor in the array which is self-aligned to the buried strap connection of the storage trench (VERI BEST) and bounded by trench isolation oxide. The VERI BEST cell concept, process and electrical results obtained from 8F/sup 2/ test cell arrays at 0.175 /spl mu/m groundrules are described in this paper.