A Fast Locking Charge-Pump PLL with Adaptive Bandwidth

Abstract

Design of bandwidth adaptive phase-locked loops (PLL) to achieve fast locking is presented in this paper. The proposed topology uses only one adaptive phase frequency detector (PFD) and controllable charge pumps to realize adaptive bandwidth scheme. With a SMIC standard 0.25/spl mu/m 1P5M 2.5V CMOS logic process, the measured results show that the experimental chip has properties of fast locking less than 4 /spl mu/s and low power consumption about 18mW.