Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

Abstract

We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</sub> ≤25nm, H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</sub> ~22nm), with increased doping enabling ION improvement without I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> penalty for W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</sub> ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> mismatch performance shows higher A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</sub> with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (d <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</sub> ≥20-30nm), integrated on the same 300mm Si platform as lateral devices. Low I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.