Achieving Sub-ns switching of STT-MRAM for future embedded LLC applications through improvement of nucleation and propagation switching mechanisms

Abstract

We present recent advances in writing speed of pSTT_MRAM which demonstrate its potential as a candidate for replacement of LCC cache for advanced technology nodes as well as applications where non-volatility may be needed. In this paper we explore the feasibility of sub-ns switching of devices and their characterization using comprehensive time resolved electrical measurement of the reversal mechanism. We show that the switching mechanism can be described as a simple nucleation followed by propagation model that can be characterized statistically. We further demonstrate that after optimization of the Magnetic Tunnel Junction (MTJ) stack, single devices can be switched reliably using write pulse length down to 750ps while preserving functionality and data retention @ 125°C. Results of the integration at array level on an 8MB test vehicle are also presented allowing full array writing using 3ns pulses without ECC and demonstrated data retention of 10 years (1ppm) at 125°C.