Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling

Abstract

In low cost vertical resistive switching memory (VRRAM), the inter-layer leakage becomes a serious problem, primarily resulting from the ultimate scaling in the vertical dimension. In this work, for the first time, we present a novel approach of fabricating 3D VRRAM using self-aligned self-selective RRAM to effectively address such challenge. By successfully suppressing the inter-layer leakage, the scaling limit of VRRAM could be extended beyond 5 nm. Other benefits, such as high nonlinearity (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ), low power consumption (sub-μA), robust endurance and excellent disturbance immunity, were also demonstrated.