A Room Temperature Flip-Chip Technology for High Pixel Count Micro-Displays and Imaging Arrays

Abstract

This paper highlights the limits that may be encountered when thermally assembling large chips having substantial mismatches of their thermal expansion coefficient (CTE). First, a theory is proposed that shows the size limitation of "emitting" or "imaging" flip-chipped devices depends on DCTE and is independent of the pixel's pitch. Secondly, a room-temperature flip-chip technique is presented that overrides these limitations: it involves an insertion of Gold capped micro-tubes inside soft Indium pads. It proves to be efficient for very high pin count assemblies at very fine pitches. The technique shows remarkably good interconnection yields on an exploratory test bed with 4 million pixels. The chips design, fabrication, assembly process, reliability process are detailed. The electrical results after flip-chip and their evolution during a standard reliability stress sequence are also analyzed. Finally, optical devices stacked on their silicon driving (CMOS) circuit at a 10 μm connection pitch are presented: Large LEDCMOS emitting array. Large IRCMOS detecting array.