IEEE Journal of Solid-State Circuits · 2016 · 95 citations · 40 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignLow-noise Circuit DesignPower AmplifiersPower ManagementPower OptimizationRadio-frequency Integrated CircuitsBluetooth Low EnergyCmos Radio-frequency CircuitsLow-power Cmos DesignLow-voltage Cmos DesignRf Cmos DesignThreshold VoltageTransmitter DesignUltra-low-power Cmos
We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.
40