Characterization of an n-Type 4-kV GTO for Pulsed Power Applications

Abstract

This paper details the experimental evaluation and simulation of a 4-kV n-type gate turn-OFF thyristor (GTO) designed for pulsed power applications. The primary criteria of evaluation are rate of current rise (dI/dt), turn-ON delay time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ), and resistance of the device during turn-ON transients [R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> (t)]. The device under test (DuT) is an n-type asymmetric-blocking GTO manufactured by Silicon Power (Part No. 14N40A10) with a rated dc blocking voltage of 4 kV. A test circuit was specifically designed to minimize stray inductance in order to capitalize on the dI/dt capabilities of the DuT. Experimental data collected from resistance measurements are used to develop a single-switch approximate model for use in simulation. The results of dI/dt experiments provide a profile of DuT dI/dt operation beyond rated values; specifically dI/dt values >70 kA/μs were readily achieved. The turn-ON delay time of the DuT is also characterized and determined to be ~225 ns on average.