Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers

Abstract

Three-dimensional (3D) integration with through-die vias offer improved electrical performance compared to edgeconnected wire bonds in stacked-die assemblies. Monolithic wafer-level 3D integration offers the potential for a high density of micron-sized through-die vias necessary for highest performance of integrated systems. In addition, such wafer-level technologies offer the potential of lowest cost in large manufacturing volume of any heterogeneous integration platform, incorporating the inherent low cost of monolithic IC interconnectivity. After a brief summary of current 3D integration technologies, a recently introduced platform that offers the process integration advantage of copper-to-copper (Cu-to-Cu) bonding with the increased adhesion strength and robustness of dielectric adhesive bonding using benzocyclobutene (BCB) is discussed. Critical processing challenges of the new platform include BCB partial curing compatible with damascene patterning, post-damascene-patterning cleaning and surface activation, bonding process parameters, and wafer-level planarization requirements. The inherent incorporation of a redistribution layer into the bonding layer process further reduces the process flow and is compatible with waferlevel packaging (WLP) technologies.